D A T A S H E E T
AC CHARACTERISTICS
tCEZ
7 cycles for initial access shown.
tCAS
CE#
1
2
3
4
5
6
7
CLK
tAVC
AVD#
tAVD
tAAS
tBDH
Addresses
Data
Aa
tBACC
tAAH
Hi-Z
tIACC
Da
Da + 1
Da + n
tACC
tOEZ
OE#
RDY
tRACC
tCR
tOE
Hi-Z
Hi-Z
tRDYS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, two additional clock cycle are inserted, and is indicated by RDY.
3. The device is in synchronous mode.
Figure 18. Synchronous Burst Mode Read
7
cycles for initial access shown.
tCES
CE#
CLK
1
2
3
4
5
6
7
tAVC
AVD#
tAVD
tACS
tBDH
A6
Addresses
Data
tBACC
tACH
tIACC
tACC
D6
D7
D0
D1
D5
D6
OE#
RDY
tCR
tRACC
tOE
Hi-Z
tRDYS
Note: Figure assumes 7 wait states for initial access and automatic detect synchronous read. D0–D7 in data waveform indicate
the order of data within a given 8-word address range, from lowest to highest. Starting address in figure is the 7th address in
range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register command sequence
has been written with A18=1; device will output RDY with valid data.
Figure 19. 8-word Linear Burst with Wrap Around
May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
59
SPANSION [ SPANSION ]
