D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data
V
IH
CLK
V
IL
tAVDP
AVD#
tAH
tAS
PA
VA
VA
Addresses
Data
555h
In
Complete
A0h
PD
tDS
tDH
Progress
CE#f
tCH
OE#
WE#
tWP
tWHWH1
tCS
tWPH
tWC
tVCS
VCC
f
Notes:
1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.
2. “In progress” and “complete” refer to status of program operation.
3. Amax–A12 are don’t care during command sequence unlock cycles.
4. CLK can be either VIL or VIH.
5. The Asynchronous programming operation is independent of the Set Device Read Mode bit in the Configuration Register.
Figure 34. Asynchronous Program Operation Timings: AVD# Latched Addresses
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Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006