D A T A S H E E T
AC CHARACTERISTICS)
Address boundary occurs every 64 words, beginning at address
00003Fh: 00007Fh, 0000BFh, etc.) Address 000000h is also a boundary crossing.
C60
C61
3D
C62
3E
C63
3F
C63
3F
C63
3F
C64
40
C65
41
C66
42
C67
43
CLK
3C
Address (hex)
(stays high)
AVD#
RDY(1)
RDY(2)
tRACC
tRACC
latency
tRACC
tRACC
latency
Data
D60
D61
D62
D63
D64
D65
D66
D67
Notes:
1. RDY active with data (A18 = 0 in the Configuration Register).
2. RDY active one clock cycle before data (A18 = 1 in the Configuration Register).
3. Cxx indicates the clock that triggers Dxx on the outputs; for example, C60 triggers D60. Figure shows the device not crossing
a bank in the process of performing an erase or program.
4. If the starting address latched in is either 3Eh or 3Fh (or some 64 multiple of either), there is no additional 2 cycle latency at
the boundary crossing.
Figure 46. Latency with Boundary Crossing
80
Am29BDS128H/Am29BDS640H
27024B3 May 10, 2006
SPANSION [ SPANSION ]
