AC CHARACTERISTICS
CLK
ADV#
CE#
tCS
Stable Address
tCH
A18
-A0
tWC
Valid Data
DQ31 DQ0
-
tAH
tAS
tDH
tDS
WE#
OE#
tOEH
tWPH
IND/WAIT#
Figure 17. Asynchronous Command Write Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.
CE#
tCES
CLK
tADVCS
tADVP
ADV#
tACS
tACH
tACH
Valid Address
tWC
t
tACS
AS
A18
-A0,
Valid Address
WORD#
tEHQZ
tADVCH
Data In
Data Out
DQ31-DQ0
tDF
tWCKS
tDH
tWADVH
tOE
OE#
WE#
tDS
tWP
10 ns
IND/WAIT#
Figure 18. Synchronous Command Write/Read Timing
Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.
June 7, 2006
Am29BDD160G
61
SPANSION [ SPANSION ]
