TEST CONDITIONS
Table 24. Test Specifications
54D,
Test Condition
Output Load
64C
65A Unit
Device
Under
Test
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
100
pF
C
L
Input Rise and Fall Times
Input Pulse Levels
5
ns
0.0 V – VIO
V
Input timing measurement
reference levels
VIO/2
V
V
Note: Diodes are IN3064 or equivalent
Figure 12. Test Setup
Output timing measurement
reference levels
VIO/2
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
SWITCHING WAVEFORMS
VIO
VIO/2 V
VIO/2 V
Input
Measurement Level
Output
VSS
Figure 13. Input Waveforms and Measurement Levels
56
Am29BDD160G
June 7, 2006
SPANSION [ SPANSION ]
