the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 23 to compare outputs for
DQ2 and DQ6.
START
Read Byte
(DQ0-DQ7)
Address = VA
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 25 shows the toggle bit timing dia-
gram. Figure 25 shows the differences between DQ2
and DQ6 in graphical form. Figure 27 shows the timing
diagram for synchronous DQ2 toggle bit status.
Read Byte
(DQ0-DQ7)
Address = VA
(Note 1)
No
DQ6 = Toggle?
Reading Toggle Bits DQ6/DQ2
Refer to Figure 25 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must perform two immediately consecutive
reads of DQ7–DQ0 to determine whether a toggle bit
is toggling. Typically, the system would note and store
the value of the toggle bit after the first read. After the
second read, the system would compare the new
value of the toggle bit with the first. If the toggle bit is
not toggling, the device has completed the program or
erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
Yes
No
DQ5 = 1?
Yes
Read Byte Twice
(DQ 0-DQ7)
Adrdess = VA
(Notes
1, 2)
However, if after the initial two immediately consecutive
read cycles, the system determines that the toggle bit
is still toggling, the system also should note whether
the value of DQ5 is high (see the section on DQ5). If it
is, the system should then determine again whether the
toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device has successfully com-
pleted the program or erase operation. If it is still tog-
gling, the device did not complete the operation
successfully, and the system must write the reset com-
mand to return to reading array data.
No
DQ6 = Toggle?
Yes
FAIL
PASS
Notes:
1. Read toggle bit with two immediately consecutive reads
to determine whether or not it is toggling. See text.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 7).
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 7. Toggle Bit Algorithm
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
June 7, 2006
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