Burst Access Timing Control
with the exception that data is valid after the falling
edge.
In addition to the IND/WAIT# signal control, burst con-
trols exist in the Control Register for initial access de-
lay, delivery of data on the CLK edge, and the length
of time data is held.
Table 8. Burst Initial Access Delay
InitialBurstAccess
(CLK cycles)
Initial Burst Access Delay Control
54D,
The Am29BDD160 contains options for initial access
delay of a burst access. The initial access delay has
no effect on asynchronous read operations.
CR13
CR12
CR11
CR10
64C, 65A
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
8
9
Burst Initial Access Delay is defined as the number of
clock cycles that must elapse from the first valid clock
edge after ADV# assertion (or the rising edge of
ADV#) until the first valid CLK edge when the data is
valid.
The burst access is initiated and the address is
latched on the first rising CLK edge when ADV# is ac-
tive or upon a rising ADV# edge, whichever comes
first. (See Table 8 describes the initial access delay
configurations.) If the Clock Configuration bit in the
Control Register is set to falling edge (CR6 = 0), the
definition remains the same for the initial delay setting
1st CLK
2nd CLK
3rd CLK
4th CLK
5th CLK
CLK
ADV#
Address 1 Latched
Valid Address
A18-A0
Three CLK Delay
3
DQ31
-
DQ0
D0
D1
D0
D2
D1
D3
D4
Four CLK Delay
4
DQ31
-
DQ0
D2
D3
Five CLK Delay
5
D0
D1
D2
DQ31-DQ0
Figure 3. Initial Burst Delay Control
Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or Five clock cycles
June 7, 2006
Am29BDD160G
21
SPANSION [ SPANSION ]
