tions and to Figure 15 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
VersatileI/O™ (VIO) Control
The VersatileI/O (VIO) control allows the host system
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on the
VIO pin.
Simultaneous Read/Write
Operations Overview and Restrictions
The output voltage generated on the device is deter-
mined based on the VIO (VCCQ) level.
Overview
Simultaneous Operation is an advances functionality
providing enhanced speed and flexibility with minimum
overhead. Simultaneous Operation does this by allow-
ing an operation to be executed (embedded operation)
in a bank (busy bank), then going to the other bank
(non-busy bank) and performing desired operations.
A VIO of 1.65–1.95 volts is targeted to provide for I/O
tolerance at the 1.8 volt level.
A VCC and VIO of 2.5–2.75 volts makes the device ap-
pear as 2.5 volt-only.
Address/Control signals are 3.6 V tolerant with the ex-
ception of CLK.
The BDD160’s Simultaneous Operation has been opti-
mized for applications that could most benefit from this
capability. These applications store code in the big
bank, while storing data in the small bank. The best
example of this is when a Sector Erase Operation (as
an embedded operation) in the small (busy) bank,
while performing a Burst/synchronous Read Operation
in the big (non-busy) bank.
Word/Double Word Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or double word configuration.
If the WORD# pin is set at VIH, the device is in double
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
Restrictions
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31–DQ16 are tri-stated.
The BDD160’s Simultaneous Operation is tested by
executing an embedded operation in the small (busy)
bank while performing other operations in the big
(non-busy) bank. However, the opposite case is nei-
ther tested nor valid. That is, it is not tested by execut-
ing an embedded operation in the big (busy) bank
while performing other operations in the small
(non-busy) bank. See Table 2 Bank assignment for
Boot Bank Sector Devices.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH.
Table 2. Bank Assignment for Boot Bank
Sector Devices
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Bottom Boot Sector
Top Boot Sector Devices
Small Bank
Devices
Bank
1
Big Bank
Bank
2
Big Bank
Small Bank
Also see Table 18, “Allowed Operations During
Erase/Program Suspend,” on page 38. Also see
Table 12, “Sector Addresses for Top Boot Sector De-
vices,” on page 29 and see Table 13, “Sector Ad-
dresses for Bottom Boot Sector Devices,” on page 30.
Address access time (tACC) is the delay from stable ad-
dresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and sta-
ble CE# to valid data at the output pins. The output en-
able access time (tOE) is the delay from the falling
edge of OE# to valid data at the output pins (assuming
the addresses have been stable for at least tACC–tOE
time and CE# has been asserted for at least tCE–tOE
time).
Simultaneous Read/Write Operations With
Zero Latency
The device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Refer to the DC Characteristics table for
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
June 7, 2006
Am29BDD160G
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