AC CHARACTERISTICS
Burst Mode Read
Parameter
Speed Options
64C
JEDEC
Std.
Description
54D
65A
Unit
Asynchronous Access Time ADV# Valid Clock
to Output Delay (See Note)
tIACC
Max
Max
Min
54
64
67
ns
9 FBGA 9.5 10 FBGA 10
tBACC
Burst Access Time Valid Clock to Output Delay
17
7
ns
ns
PQFP
PQFP
ADV# Setup Time to Rising (Falling) Edge of
CLK
tADVCS
4
5
tADVCH ADV# Hold Time
Min
Min
Max
Min
2
ns
ns
ns
ns
tADVP
tBDH
ADV# Pulse Width
15
2
15
4
18
Data Hold Time from Next Clock Cycle
Valid Data Hold from CLK
tDVCH
3
3
9 FBGA 9.5 10 FBGA 10
tDIND
CLK to Valid IND/WAIT#
Max
17
ns
PQFP
PQFP
tINDH
tIACC
IND/WAIT# Hold from CLK
Min
Max
Min
Max
Max
Max
Min
Min
Min
2
3
3
ns
ns
CLK to Valid Data Out, Initial Burst Access
54
60
18
60
3
68
25
15
tCLK
CLK Period
ns
tCR
tCF
tCH
tCL
tCH
CLK Rise Time
CLK Fall Time
CLK High Time
CLK Low Time
CE# Hold Time
ns
ns
ns
ns
ns
3
2.5
2.5
3
2.5
2.5
3
3
tACS
Address Setup Time to CLK (See Note)
Min
Min
5
1
6
2
7
2
ns
Address Hold Time from ADV# Rising Edge
(See Note)
tACH
tOE
ns
ns
Output Enable to Output Valid
Max
Min
20
3
2
10
10
4
3
17
17
6
tDF
tOEZ
Output Enable to Output High Z
ns
Max
Max
Min
15
15
5
tEHQZ
tCEZ
tCES
Chip Enable to Output High Z
CE# Setup Time to Clock
ns
ns
Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. tIACC may also be calculated using the
following formula: tIACC = (clock delays) x (clock period) + tBACC
.
June 7, 2006
Am29BDD160G
59
SPANSION [ SPANSION ]
