DATA SHEET
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode,
Dual Boot, Simultaneous Read/Write Flash Memory
NOTE: For new designs, S29CD016G supersedes Am29BDD160G and is the factory-recommended migration path for this device. Please refer to the S29CD016G datasheet for specifica-
tions and ordering information.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— Burst Mode Read: 90 mA @ 66 MHz max
— Program/Erase: 50 mA max
Simultaneous Read/Write operations
— Standby mode: CMOS: 60 µA max
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
(–40°C to 85°C, 56 MHz and below only)
Minimum 1 million write cycles guaranteed per
sector
— Zero latency between read and write operations
— Two bank architecture: 75%/25%
User-Defined x16 or x32 Data Bus
Dual Boot Block
20 year data retention at 125°C
VersatileI/OTM control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
— Top and bottom boot in the same device
Flexible sector architecture
— 1.65 V to 2.75 V compatible I/O signals
— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes
sectors
SOFTWARE FEATURES
Persistent Sector Protection
Manufactured on 0.17 µm process technology
SecSi (Secured Silicon) Sector (256 Bytes)
— A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector (requires only VCC levels)
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
Password Sector Protection
— Factory locked and identifiable: 16 bytes for secure,
random factory Electronic Serial Number; remainder
may be customer data programmed by AMD
— A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-definable 64-bit password
— Customer lockable: Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
Programmable Burst interface
— Reduces overall programming time when issuing
multiple program command sequences
— Interface to any high performance processor
— Modes of Burst Read Operation:
Linear Burst: 4 double words (x32), 8 words (x16)
and double words (x32), and 32 words (x16) with
wrap around
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Single power supply operation
HARDWARE FEATURES
— Optimized for 2.5 to 2.75 volt read, erase, and
program operations
Program Suspend/Resume & Erase
Suspend/Resume
Compatible with JEDEC standards (JC42.4)
— Suspends program or erase operations to allow
reading, programming, or erasing in same bank
— Pinout and software compatible with
single-power-supply flash standard
Hardware Reset (RESET#), Ready/Busy# (RY/BY#),
and Write Protect (WP#) inputs
PERFORMANCE CHARACTERISTICS
ACC input
High performance read access
— Initial/random access time as fast as 54 ns
— Accelerates programming time for higher throughput
during system production
— Burst access time as fast as 9 ns for ball grid array
package
Package options
— 80-pin PQFP
Ultra low power consumption
— 80-ball Fortified BGA
Publication# 24960 Rev: D Amendment: 5
Issue Date: June 7, 2006
Refer to AMD’s Website (www.amd.com) for the latest information.
SPANSION [ SPANSION ]
