controlled internal to the device. Typical erasure at room
temperature is accomplished in 1.5 seconds, including
preprogramming.
AMD’s Am28F256A is entirely pin and software com-
patible with AMD’s Am28F020A, Am28F256A and
Am28F512A Flash memories.
Comparing Embedded Algorithms with Flasherase and Flashrite Algorithms
Am28F256A with
Embedded Algorithms
Am28F256 using AMD Flashrite
and Flasherase Algorithms
Embedded
Programming
Algorithm vs.
Flashrite
Programming
Algorithm
AMD’s Embedded Programming algorithm
requires the user to only write a program
set-up command and a program command
(program data and address). The device
automatically times the programming
pulse width, verifies the programming, and
counts the number of sequences. A status
bit, Data# Polling, provides the user with
the programming operation status.
The Flashrite Programming algorithm requires the
user to write a program set-up command, a program
command, (program data and address), and a
program verify command, followed by a read and
compare operation. The user is required to time the
programming pulse width in order to issue the
program verify command. An integrated stop timer
prevents any possibility of overprogramming.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
the data intended to be written; if there is not a
match, the sequence is repeated until there is a
match or the sequence has been repeated 25 times.
Embedded Erase
Algorithm vs.
Flasherase Erase
Algorithm
AMD’s Embedded Erase algorithm
requires the user to only write an erase set- to be completely programmed prior to executing an
The Flasherase Erase algorithm requires the device
up command and erase command. The
device automatically pre-programs and
verifies the entire array. The device then
automatically times the erase pulse width,
verifies the erase operation, and counts
the number of sequences. A status bit,
Data# Polling, provides the user with the
erase operation status.
erase command.
To invoke the erase operation, the user writes an
erase set-up command, an erase command, and an
erase verify command. The user is required to time
the erase pulse width in order to issue the erase
verify command. An integrated stop timer prevents
any possibility of overerasure.
Upon completion of this sequence, the data is read
back from the device and compared by the user with
erased data. If there is not a match, the sequence is
repeated until there is a match or the sequence has
been repeated 1,000 times.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and
erase operations. For system design simplification, the
Am28F256A is designed to support either WE# or CE#
controlled writes. During a system write cycle,
addresses are latched on the falling edge of WE# or
CE# whichever occurs last. Data is latched on the rising
edge of WE# or CE# whichever occurs first. To simplify
the following discussion, the WE# pin is used as the
write cycle control pin throughout the rest of this text. All
setup and hold times are with respect to the WE# signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are
programmed one byte at a time using the EPROM
programming mechanism of hot electron injection.
2
Am28F256A
SPANSION [ SPANSION ]
