AC CHARACTERISTICS
Parameter Symbols
Am27X128
JEDEC Standard
Description
Address to Output Delay
Test Setup
CE#,
-55
55
55
35
-70
70
70
40
-90 -120 -150 -200 -255 Unit
t
t
t
Max
90
90
40
120 150 200 250
120 150 200 250
ns
ns
ns
AVQV
ELQV
GLQV
ACC
OE# = V
IL
t
Chip Enable to Output Delay OE# = V Max
CE
OE
IL
Output Enable to Output
Delay
t
t
CE# = V Max
50
30
50
30
50
30
50
30
IL
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
t
t
t
EHQZ
GHQZ
DF
Max
Min
25
0
25
0
25
0
ns
ns
(Note 2)
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
t
t
0
0
0
0
AXQX
OH
Caution: Do not remove the device from (or insert it into) a socket or board that has V or V applied.
PP
CC
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
PP
CC
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses
0.45
Addresses Valid
CE#
t
CE
OE#
t
(Note 2)
DF
t
OE
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
12083F-9
Notes:
1. OE# may be delayed up to t
– t after the falling edge of the addresses without impact on t .
ACC
ACC
OE
2. t is specified from OE# or CE#, whichever occurs first.
DF
PACKAGE CAPACITANCE
PD 028
PL 032
Parameter
Symbol
Parameter Description
Input Capacitance
Test Conditions
Typ
Max
10
Typ
10
Max
12
Unit
pF
C
V
V
= 0
5
8
IN
IN
C
Output Capacitance
= 0
10
11
14
pF
OUT
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
8
Am27X128
SPANSION [ SPANSION ]
