AC CHARACTERISTICS
Parameter Symbols
Am27C512
JEDEC Standard
Description
Test Setup
-55 -70 -90 -120 -150 -200 -255 Unit
CE#,
OE# = V
t
t
t
Address to Output Delay
Max
55
70
90 120 150 200 250
90 120 150 200 250
ns
AVQV
ACC
IL
IL
IL
t
Chip Enable to Output Delay
OE# = V
Max
Max
55
35
70
40
ns
ns
ELQV
GLQV
CE
t
t
Output Enable to Output Delay CE# = V
40
50
50
75
75
OE
Chip Enable High or Output
Enable High to Output High Z,
Whichever Occurs First
t
t
t
EHQZ
GHQZ
DF
Max
Min
25
0
25
0
25
30
30
30
30
ns
ns
(Note 2)
Output Hold Time from
Addresses, CE# or OE#,
Whichever Occurs First
t
t
0
0
0
0
0
AXQX
OH
Caution: Do not remove the device from (or insert it into) a socket or board that has V or V applied.
PP
CC
Notes:
1. V must be applied simultaneously or before V , and removed simultaneously or after V .
PP
CC
PP
2. This parameter is sampled and not 100% tested.
3. Switching characteristics are over operating range, unless otherwise specified.
4. See Figure 3 and Table 1 for test specifications.
SWITCHING WAVEFORMS
2.4
2.0
0.8
2.0
0.8
Addresses
0.45
Addresses Valid
CE#
OE#
t
CE
t
(Note 2)
DF
t
OE
t
ACC
t
OH
(Note 1)
High Z
High Z
Output
Valid Output
08140J-9
Notes:
1. OE# may be delayed up to t
– t after the falling edge of the addresses without impact on t .
ACC
ACC
OE
2. t is specified from OE# or CE#, whichever occurs first.
DF
PACKAGE CAPACITANCE
CDV028
PL 032
Typ Max
PD 028
Parameter
Parameter Symbol
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ
Max
12
Typ
Max
10
Unit
pF
C
V
V
= 0
10
10
9
9
12
12
6
6
IN
IN
OUT
C
= 0
13
10
pF
OUT
Notes:
1. This parameter is only sampled and not 100% tested.
2. T = +25°C, f = 1 MHz.
A
10
Am27C512
SPANSION [ SPANSION ]
