TEST CONDITIONS
5.0 V
Table 1.
Test Specifications
All
1 TTL gate
100
≤
20
0.45–2.4
0.8, 2.0
0.8, 2.0
pF
ns
V
V
V
Unit
Test Condition
Device
Under
Test
CL
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement reference
levels
2.7 kΩ
Output Load
Output Load Capacitance, C
L
(including jig capacitance)
Note:
Diodes are IN3064 or equivalents.
11408F-7
Output timing measurement
reference levels
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
2.4 V
2.0 V
Test Points
0.8 V
0.45 V
Input
Output
0.8 V
2.0 V
Note:
For C
L
= 100 pF.
11408F-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
KS000010-PAL
Am27C4096
9
SPANSION [ SPANSION ]
