TEST CONDITIONS
5.0 V
Table 1.
Test Condition
Output Load
Test Specifications
-55
All
others
1 TTL gate
30
≤
20
0.0–3.0 0.45–2.4
1.5
1.5
0.8, 2.0
0.8, 2.0
100
pF
ns
V
V
V
Unit
Device
Under
Test
CL
6.2 kΩ
2.7 kΩ
Output Load Capacitance, C
L
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Note:
Diodes are IN3064 or equivalents.
06780J-7
Input timing measurement
reference levels
Output timing measurement
reference levels
Figure 3.
Test Setup
SWITCHING TEST WAVEFORM
3V
1.5 V
0V
Input
Output
Test Points
1.5 V
0.8 V
0.45 V
Input
Output
2.4 V
2.0 V
Test Points
0.8 V
2.0 V
Note:
For C
L
= 30 pF.
Note:
For C
L
= 100 pF.
06780J-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
OUTPUTS
KS000010-PAL
Am27C1024
9
SPANSION [ SPANSION ]
