TEST CONDITIONS
5.0 V
Table 1. Test Specifications
Test Condition -55 All
1 TTL gate
Unit
2.7 kΩ
Output Load
Device
Under
Test
Output Load Capacitance, C
(including jig capacitance)
L
30
100
pF
C
L
6.2 kΩ
Input Rise and Fall Times
Input Pulse Levels
≤ 20
0.0–3.0 0.45–2.4
ns
V
Input timing measurement
reference levels
1.5
1.5
0.8, 2.0
0.8, 2.0
V
V
Note:
Output timing measurement
reference levels
Diodes are IN3064 or equivalents.
11507J-7
Figure 3. Test Setup
SWITCHING TEST WAVEFORM
3 V
2.4 V
2.0 V
2.0 V
Test Points
1.5 V
Test Points
1.5 V
0.8 V
0.8 V
0 V
0.45 V
Input
Output
Input
Output
Note: For C = 30 pF.
Note: For C = 100 pF.
L
L
11507J-8
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Does Not Apply
Changing, State Unknown
Center Line is High Impedance State (High Z)
KS000010-PAL
Am27C020
9
SPANSION [ SPANSION ]
