D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29LV400B Device Bus Operations
DQ8–DQ15
DQ0– BYTE# BYTE#
Addresses
(Note 1)
Operation
CE# OE# WE# RESET#
DQ7
DOUT
DIN
= VIH
DOUT
DIN
= VIL
Read
Write
L
L
L
H
L
H
H
AIN
AIN
DQ8–DQ14=High-Z,
DQ15 = A-1
H
VCC
0.3 V
VCC
0.3 V
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
Sector Address, A6 = L,
A1 = H, A0 = L
Sector Protect (Note 2)
L
L
X
H
H
X
L
L
X
VID
VID
VID
DIN
DIN
DIN
X
X
X
X
Sector Address, A6 = H,
A1 = H, A0 = L
Sector Unprotect (Note 2)
Temporary Sector
Unprotect
AIN
DIN
High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
The internal state machine is set for reading array data
Word/Byte Configuration
upon device power-up, or after a hardware reset. This
The BYTE# pin controls whether the device data I/O
ensures that no spurious alteration of the memory
pins DQ15–DQ0 operate in the byte or word configura-
content occurs during the power transition. No com-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
mand is necessary in this mode to obtain array data.
word configuration, DQ15–DQ0 are active and con-
Standard microprocessor read cycles that assert valid
trolled by CE# and OE#.
addresses on the device address inputs produce valid
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
data on the device data outputs. The device remains
enabled for read access until the command register
contents are altered.
Address access time (tACC) is the delay from stable ad-
dresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and sta-
ble CE# to valid data at the output pins. The output en-
able access time (tOE) is the delay from the falling
edge of OE# to valid data at the output pins (assuming
the addresses have been stable for at least
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
tACC–tOE time).
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
December 4, 2006 21523D4
Am29LV400B
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