D A T A S H E E T
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std Description
Test Setup
55R
70
90
120
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
55
70
90
120
ns
CE# = VIL
OE# = VIL
tAVQV
tACC Address to Output Delay
Max
55
70
90
120
ns
tELQV
tGLQV
tEHQZ
tGHQZ
tCE
tOE
tDF
tDF
Chip Enable to Output Delay
OE# = VIL Max
55
30
70
30
90
35
120
50
ns
ns
ns
ns
ns
Output Enable to Output Delay
Max
Max
Max
Min
Chip Enable to Output High Z (Note 1)
Output Enable to Output High Z (Note 1)
16
16
0
Read
Output Enable
Hold Time (Note 1)
tOEH
Toggle and
Data# Polling
Min
Min
10
0
ns
ns
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
tAXQX
tOH
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 7 for test specifications.
tRC
Addresses Stable
tACC
Addresses
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0 V
Figure 13. Read Operations Timings
28
Am29LV400B
21523D4 December 4, 2006
SPANSION [ SPANSION ]
