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AM26LV400BT-55RWAK 参数 Datasheet PDF下载

AM26LV400BT-55RWAK图片预览
型号: AM26LV400BT-55RWAK
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K的×8位/ 256千×16位) CMOS 3.0伏只引导扇区闪存 [4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory]
分类和应用: 闪存
文件页数/大小: 48 页 / 1129 K
品牌: SPANSION [ SPANSION ]
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D A T A S H E E T  
program or erase operation. If it is still toggling, the de-  
status check, the last command might not have been  
accepted. Table 6 shows the outputs for DQ3.  
vice did not completed the operation successfully, and  
the system must write the reset command to return to  
reading array data.  
The remaining scenario is that the system initially de-  
termines that the toggle bit is toggling and DQ5 has  
not gone high. The system may continue to monitor  
the toggle bit and DQ5 through successive read cy-  
cles, determining the status as described in the previ-  
ous paragraph. Alternatively, it may choose to perform  
other system tasks. In this case, the system must start  
at the beginning of the algorithm when it returns to de-  
termine the status of the operation (top of Figure 6).  
START  
Read DQ7–DQ0  
(Note 1)  
Read DQ7–DQ0  
DQ5: Exceeded Timing Limits  
DQ5 indicates whether the program or erase time has  
exceeded a specified internal pulse count limit. Under  
these conditions DQ5 produces a “1.This is a failure  
condition that indicates the program or erase cycle  
was not successfully completed.  
No  
Toggle Bit  
= Toggle?  
Yes  
The DQ5 failure condition may appear if the system  
tries to program a “1” to a location that is previously  
programmed to “0.Only an erase operation can  
change a “0” back to a “1.Under this condition, the  
device halts the operation, and when the operation  
has exceeded the timing limits, DQ5 produces a “1.”  
No  
DQ5 = 1?  
Yes  
Under both these conditions, the system must issue  
the reset command to return the device to reading  
array data.  
(Notes  
1, 2)  
Read DQ7–DQ0  
Twice  
DQ3: Sector Erase Timer  
After writing a sector erase command sequence, the  
system may read DQ3 to determine whether or not an  
erase operation has begun. (The sector erase timer  
does not apply to the chip erase command.) If addi-  
tional sectors are selected for erasure, the entire  
time-out also applies after each additional sector  
erase command. When the time-out is complete, DQ3  
switches from “0” to “1.If the time between additional  
sector erase commands from the system can be as-  
sumed to be less than 50 µs, the system need not  
monitor DQ3. See also the “Sector Erase Command  
Sequence” section.  
Toggle Bit  
= Toggle?  
No  
Yes  
Program/Erase  
Operation Not  
Complete, Write  
Reset Command  
Program/Erase  
Operation Complete  
Notes:  
1. Read toggle bit twice to determine whether or not it is  
toggling. See text.  
After the sector erase command sequence is written,  
the system should read the status on DQ7 (Data# Poll-  
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-  
cepted the command sequence, and then read DQ3. If  
DQ3 is “1”, the internally controlled erase cycle has  
begun; all further commands (other than Erase Sus-  
pend) are ignored until the erase operation is com-  
plete. If DQ3 is “0”, the device will accept additional  
sector erase commands. To ensure the command has  
been accepted, the system software should check the  
status of DQ3 prior to and following each subsequent  
sector erase command. If DQ3 is high on the second  
2. Recheck toggle bit because it may stop toggling as DQ5  
changes to “1”. See text.  
Figure 6. Toggle Bit Algorithm  
22  
Am29LV400B  
21523D4 December 4, 2006