D at a
S hee t
5.2
5.2.1
Connection Diagrams
CellularRAM Based Pinout
84-ball Fine-Pitch Ball Grid Array
CellularRAM-based Pinout (Top View, Balls Facing Down)
Legend
A1
DNU
B2
AVD#
C2
F-WP#
D2
A3
E2
A2
F2
A1
G2
A0
H2
F1-CE#
J2
R-CE1#
K2
RFU
L2
RFU
M1
DNU
B3
RFU
C3
A7
D3
A6
E3
A5
F3
A4
G3
V
SS
H3
OE#
J3
DQ0
K3
DQ8
L3
RFU
B4
CLK
C4
R-LB#
D4
B5
F2-CE#
C5
ACC
D5
B6
RFU
C6
WE#
D6
RFU
E6
A20
F6
A23
G6
RFU
H6
DQ4
J6
R-VCC
K6
RFU
L6
RFU
B7
RFU
C7
A8
D7
A19
E7
A9
F7
A10
G7
DQ6
H7
DQ13
J7
DQ12
K7
DQ5
L7
RFU
B8
RFU
C8
A11
D8
A12
E8
A13
F8
A14
G8
RFU
H8
DQ15
J8
DQ7
K8
DQ14
L8
RFU
B9
RFU
C9
RFU
D9
A10
DNU
Shared
Flash Shared only
1st Flash only
A15
E9
A21
F9
A22
G9
A16
H9
R-CRE
J9
V
SS
K9
RFU
L9
RFU
M10
DNU
RAM only
2nd Flash only
R-UB# F-RST#
E4
A18
F4
A17
G4
DQ1
H4
DQ9
J4
DQ10
K4
DQ2
L4
RFU
E5
RDY
F5
RFU
G5
RFU
H5
DQ3
J5
F-VCC
K5
DQ11
L5
F-VCC
Notes:
1. In MCPs based on a single S29WS256N (S71WS256N), ball B5 is RFU. In MCP's based on two S29WS256N (S71WS512), ball B5 is
F2-CE#.
2. Addresses are shared between Flash and RAM depending on the density of the pSRAM.
MCP
S71WS128NB0
S71WS128NC0
S71WS256NC0
S71WS256ND0
S71WS512NC0
S71WS512ND0
Flash-only Addresses
A22-A21
A22
A23 – A22
A23
A23 – A22
A23
Shared Addresses
A20-A0
A21-A0
A21 – A0
A22 – A0
A21-A0
A22-A0
6
S71WS-N
S71WS-N_00_A7 April 4, 2008
SPANSION [ SPANSION ]
