CXD2510Q
Timing Chart 3-3
Normal-speed PB
400 to 500ns
RFCK
t = Dependent on error
condition
MNT3
MNT2
C1 correction
C2 correction
MNT1
MNT0
Strobe
Strobe
§3-4. DA Interface
• The CXD2510Q has two modes as DA interfaces.
a) 48-bit slot interface
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
b) 64-bit slot interface
This interface includes 64 cycles of the bit clock within one LRCK cycle, and is LSB first.
When LRCK is low, the data is for the left channel.
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SONY [ SONY CORPORATION ]
