CXD2510Q
§2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read from
SBSO by inputting EXCK.
Sub Q can be read out after the CRC check of the 80 bits of information in the subcode frame.
This is accomplished, after checking SCOR and CRCF, by inputting 80 clock pulses to SQCK and reading data
from the SQSO pin.
§2-1. P to W Subcode Read
Data can be read out by inputting EXCK immediately after WFCK falls. (See the Timing Chart 2-1.)
§2-2. 80-bit Sub Q read
Fig. 2-2 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC
check circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, the 80 bits are
loaded into the parallel/serial register.
When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC
check) has been loaded.
• In the CXD2510Q, when 80-bit data is loaded, the order of the MSB and LSB is inverted for each byte. As a
result, although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the fact that the 80-bit data has been loaded is confirmed, SQCK is input so that the data can be
read. In this LSI, the SQCK input is detected, and the retriggerable monostable multivibrator is reset during
low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration that
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the S/P register is not loaded into the P/S register.
• While the monostable multivibrator is being reset, data cannot be loaded in the peak detection
parallel/serial register or the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than the monostable multivibrator time constant,
the register will not be rewritten by CRCOK and others.
• In this LSI, the previously mentioned peak detection register can be connected to the shift-in of the 80-bit
P/S register.
Input and output for ring control 1 are shorted in peak meter or level meter mode.
Ring control 2 is shorted in peak meter mode.
This is because the register is reset with each readout in level meter mode, and to prevent readout
destruction in peak meter mode.
As a result, the 96-bit clock must be input in peak meter mode.
• In addition, as previously mentioned, the absolute time after peak is generated is stored in the memory in
peak meter mode.
Fig. 2-3 shows the Timing Chart.
• Although a clock is input from the SQCK pin to actually perform these operations, the high and low intervals
for this clock should be between 750ns and 120µs.
– 26 –
SONY [ SONY CORPORATION ]
