CXA2542AQ
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be
minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ↓ ?
YES
Transfer $08
NO
NO
F. OK?
YES
F. OK?
YES
NO
NO
Transfer $08
FZC ↓ ?
YES
Latch
(A)
Latch
(B)
Fig. 5. Poor and good software command sequences
2. $1X (DFCT1 at SENS1 pin (Pin 23), DFCT2 at SENS2 pin (Pin 24))
These commands deal with switching TG1/TG2, brake circuit ON/OFF,
and the sled kick output.
Sled kick level
The bit configuration is as follows:
D1
D0
(PS1)
(PS0)
D7
0
D6
0
D5
0
D4
1
D3
D2
D1
D0
0
0
0
1
±1
±2
TG1, TG2 Brake
circuit
Sled kick
level
1
1
0
1
±3
±4
ON/OFF ON/OFF
TG1, TG2, TM7
The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked
switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track
jump has been performed actually though a 100-track jump was intended to be done due to the extremely
degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump.
For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to
the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between
the RF envelope and the tracking error is 180° out-of-phase to cut the unneeded portion of the tracking error
and apply braking.
– 31 –
SONY [ SONY CORPORATION ]
