CXA2108AQ
4. Operating modes (Upper/Lower, Upper/Lower/RGB)
The CXA2108AQ has the following two operation modes which are set by the MODE pin.
4-1. Upper/Lower mode (MODE = low)
In this mode, two LEDs are driven by time division for each IOUT output.
First, PWM waveform output starts triggered by the DLDI input signal. In this mode, two kinds of luminance
data are output by time division for each output. Labeling these data as U and L, the driver outputs the data in
the order of U → L → U → L → U → and so on. The XUPR pin output voltage switches in sync with the LED
emitting cycle Ts in the order of L → H → L → and so on, so this can be used as the FET or other switch signal
for switching the LED. (See Fig. 6. Timing Chart 2-1 and Fig. 11. Application Circuit (1) for details.)
New PWM data is output when the next DLDI signal is input.
4-2. Upper/Lower/RGB mode (MODE = high)
In this mode, six LEDs can be driven by time division for each IOUT output.
PWM waveform output starts triggered by the DLDI input signal. In this mode, six kinds of luminance data are
output by time division for each output. Labeling these data as UB, UR, UG, LB, LR and LG, the driver
switches the output in the order of UB → UR → UG → LB → LR → LG → UB → and so on. Like Upper/Lower
mode, the XUPR and also the XB, XR and XG output voltages switch in sync with Ts, so these can be used as
the FET or other switch signals for switching the LEDs. The output voltages at this time are: XUPR = low for
U , XUPR = high for L , XB = low (XR = XG = high) for B, XR = low (XB = XG = high) for R, and XG = low
(XB = XR = high) for G. (See Fig. 7. Timing Chart 2-2 and Fig. 12. Application Circuit (2) for details.)
New PWM data is output when the next DLDI signal is input.
5. Luminance data memory and DLDI signal
The CXA2108AQ uses two sets of 6-word × 24-channel × 10-bit RAM (RAM (A), RAM (B)) as luminance data
memories, and switches these memories. While the data in one memory is being loaded internally and PWM
output is being performed, the next luminance data can be written to the other memory from an external
source. Memory switching is performed by inputting a trigger signal to the DLDI pin. The read/write enabled
memory alternates from A → B → A → and so on, and the memory used for PWM output alternates from B →
A → B → and so on each time the signal is input to DLDI. The DLDI signal switches the memory, and at the
same time functions as the PWM output start trigger pulse. See the Timing Charts for details.
6. Reference current (Iref)
The drive current is generated using the current flowing to an external resistor as the reference. This resistor
Rext is connected between the REXT pin and GND. The REXT pin voltage is designed to be unaffected by
supply voltage, temperature or other fluctuations, and is always a constant voltage (approximately 1.3V).
Therefore, a constant current can be realized by using a resistor that does not have temperature
characteristics. The current obtained by dividing this current value by the number of IOUT outputs (24) is
defined as Iref.
Iref = (1.3/Rext)/24
The maximum drive current value can be changed by varying the resistance value. See Table 2. Drive Current
Setting and Power Consumption for details.
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SONY [ SONY CORPORATION ]
