CXA2101AQ
Pin
No.
Symbol
Equivalent circuit
Description
VCC
55
Input for SCL (Serial Clock) complying with
I2C bus standard.
VIH ≥ 3V
55
56
57
58
59
SCL
4k
VIL ≤ 1.5V
10k
GND
VCC
Input for SDA (Serial Data) complying with I2C
bus standard.
VIH ≥ 3V
56
SDA
4k
VIL ≤ 1.5V
VOL ≤ 0.6V
7.5k
GND
VCC
Muting of the dynamic picture (black
expansion) can be controlled by this pin.
MUTE: ON VIH ≥ 1V
57
40k
DPIC-MUTE
MUTE: OFF VIL ≤ 0.4V
GND
VCC
58
Y system clamping capacitor connecting pin.
Also used as a pin to connect the capacitor
which sets the DC transmission rate.
8k
CLP-C
GND
VCC
500
VM output.
1k
30k
The differential waveforms of the Y signal are
output with a positive polarity. Their amplitude
and phase can be adjusted by the I2C bus.
VM-OUT
59
800µA
GND
– 10 –
SONY [ SONY CORPORATION ]
