CXA2050S
Pin
No.
Symbol
Equivalent circuit
Description
Color difference signal inputs.
Clamped to 5.5V at the burst timing.
Standard input levels for 75% CB:
B-Y: 1.33Vp-p
14 – (R-Y) IN
15 – (B-Y) IN
14
15
1.5k
R-Y: 1.05Vp-p
70k
16 SGND2
GND for the RGB block.
Input which combines YS1SW control with
VM circuit ON/OFF function. Supports
with ternary.
100µA
VMSW (VthVM = 0.9V)
VILVM ≤ 0.3V VM circuit ON
VIHVM ≥ 1.5V VM circuit OFF
YS1SW (VthYS1 = 2.5V)
YS1/VM
10k
17
17
VILYS1 ≤ 1.7V Y/color difference input
selected
20k
VIHYS1 ≥ 3.3V RGB1 input selected
Setting YS1OFF of I2C bus to 1, input for
this pin is invalid.
Analog R, G and B signal inputs.
Input a 0.7Vp-p (no sync, 100 IRE) signal
via a capacitor.
The signal is clamped to 5.7V at the burst
timing of the signal input to the HSIN
input (Pin 53).
200
18
19
20
18 R1IN
19 G1IN
20 B1IN
30k
100µA
YM/YS2SW YS2 control input.
When YS2 is high, the RGB2 block signal
is selected; when YS2 is low, the YS1SW
output signal is selected.
21 YS2
21
VILMAX = 0.4V
VIHMIN = 1.0V
40k
100µA
YM/YS2 SW YM control input.
When YM is high, the YS1SW output
signal is attenuated by 6dB.
VILMAX = 0.4V
22 YM
22
VIHMIN = 1.0V
40k
– 6 –
SONY [ SONY CORPORATION ]
