CXA2050S
Pin
No.
Symbol
Equivalent circuit
Description
15k
Sync signal input for V sync separation.
Input a 2Vp-p Y signal (or a 0.6Vp-p
sync signal).
147
VSIN
52
52
4.1V
20µA
14k
Sync signal input for H sync separation.
Input a 2Vp-p Y signal (or a 0.6Vp-p sync
signal).
147
53 HSIN
53
3.2V
10µA
Sync signal output for VSIN and HSIN.
The output can be selected from the
internal sync signals (Pin 60 or Pin 62) or
the external sync signal (Pin 63) by the
I2C bus.
1.2k
40k
54 SYNCOUT
147
54
Output signal level: 2Vp-p
240µA
(0.6Vp-p sync only)
Input/output gain: 6dB
Outputs the differential waveform of the
VM (Velocity Modulation) Y signal.
The signal advanced for 200ns from
YOUT is output. The delay time versus
YIN is determined by the DL setting of
the I2C bus. This output level can be set
at 2.65Vp-p or 1.1Vp-p by the I2C bus.
Pedestal level is DC6.2V.
500
1.2k
30k
55 VM
147
55
400µA
This output can also be turned off by
YS1, YM, and YS2.
4k
I2C bus protocol SCL (Serial Clock) input.
VILMAX = 1.5V
56
56 SCL
VIHMIN = 3.5V
– 11 –
SONY [ SONY CORPORATION ]
