CXA1814N
Serial Control Block
Block connection
ATF IC
Mechanism/Servo
Controller
(MCU)
SIN
SOUT
SCLK
CS
Serial
Port
PB GAIN
SCLK
CS
Gain
Control
&
SP/LP GAIN
TESTMODE
Select
TESTMODE
Control
The 10 bits before Data Read CS rises at the rising
edge are labeled D0 to D9. (See the figure below.)
Data Read : Rising Edge
Timing chart
CS
D0 to D9 : 10BITS Before Rising Edge of CS
Tcsclk Tclk
Tclkcs
SCLK
NIN
MAX
Tcsclk 5 µsec
DataRead
Tclk
1 µsec
Tclkcs 5 µsec
SIN
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Serial Data Contents (SERIAL DATA)
GCA1 GCA2
D0 D1 D2 D3 PBAMPGAIN (dB)
TEST
D4 D5 D6 D7 SPAMPGAIN (dB)
D8 D9
TESTMODE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 ± 0.5
1 ± 0.5
2 ± 0.5
3 ± 0.5
4 ± 0.5
5 ± 0.5
6 ± 0.5
7 ± 0.5
8 ± 0.5
9 ± 0.5
10 ± 0.5
11 ± 0.5
12 ± 0.5
13 ± 0.5
14 ± 0.5
15 ± 0.5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 ± 0.5
1 ± 0.5
2 ± 0.5
3 ± 0.5
4 ± 0.5
5 ± 0.5
6 ± 0.5
7 ± 0.5
8 ± 0.5
9 ± 0.5
10 ± 0.5
11 ± 0.5
12 ± 0.5
13 ± 0.5
14 ± 0.5
15 ± 0.5
0
0
1
1
0
1
0
1
OUTPUT OF GCA
OUTPUT OF B.M
INPUT OF BPF16 k, 46 k
NOT USED
Note) For input mode, pull up to
VCC with a 100 kΩ resistor.
Input voltage is 0.5 Vp-p or
less.
Glp1M REF
(Glp1M = 25 ± 2 dB)
Grf1 REF
(Grf1 = 5 ± 2 dB)
– 16 –
SONY [ SONY CORPORATION ]
