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CXA1797 参数 Datasheet PDF下载

CXA1797图片预览
型号: CXA1797
PDF下载: 下载PDF文件 查看货源
内容描述: 有记录均衡放大器杜比BC型降噪系统 [Dolby B-C Type Noise Reduction System with Recording Equalizer Amplifier]
分类和应用: 放大器
文件页数/大小: 31 页 / 738 K
品牌: SONY [ SONY CORPORATION ]
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CXA1797Q  
Specifications  
Min. Typ. Max.  
0.08 0.3  
Block  
Item  
Conditions  
Unit  
%
DOLBY  
Dolby C total harmonic distortion REC, Dolby C mode  
Input a 1 kHz, +10 dB signal to the REC IN pin and measure  
the distortion. (Measure the distortion as THD + N.)  
REC, Dolby C mode, Rg = 5.1 kΩ  
DOLBY  
REC mode  
60.0 61.0  
dB  
Dolby C S/N ratio  
With no signal, measure the noise using the CCIR/ARM  
filter. (The measured value is indicated as the relative  
value compared to the DOLBY OUT level.)  
PB, NR off mode  
DOLBY  
DOLBY  
DOLBY  
DOLBY  
DOLBY  
PB mode  
–79 –70 dB  
–90 –70 dB  
–84 –65 dB  
–85 –65 dB  
Recording playback crosstalk Input a 1 kHz, +10 dB signal to the REC IN pin and  
measure the REC PB crosstalk. (Use a 1 kHz BPF.)  
REC mode  
REC, NR off mode  
Playback recording crosstalk Input a 1 kHz, +10 dB signal to the NR PB IN pin and  
measure the PB REC crosstalk. (Use a 1 kHz BPF.)  
REC mode  
PB, NR off mode  
Channel crosstalk  
Input a 1 kHz, +10 dB signal to the REC IN pin and  
measure the channel crosstalk. (Use a 1 kHz BPF.)  
PB, NR off mode  
PB mode  
Channel crosstalk  
Input a 1 kHz, +10 dB signal to the NR PB IN pin and  
measure the channel crosstalk. (Ues a 1 kHz BPF.)  
REC mode, NR off B type  
REC mode  
–100  
100 mV  
100 mV  
Output DC offset voltage 1  
(REC OUT pin)  
With no signal, measure the deviation in the output DC  
offset voltage at the REC OUT pin when switching from  
NR off mode to B type mode.  
DOLBY  
REC mode  
REC mode, NR off C type  
–100  
Output DC offset voltage 2  
(REC OUT pin)  
With no signal, measure the deviation in the output DC  
offset voltage at the REC OUT pin when switching from  
NR off mode to C type mode.  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
Logic  
High level input voltage  
Low level input voltage  
Clock frequency  
Clock pulse width  
Data setup time  
ViH  
3.5  
1
V
V
ViL  
1.5  
fck  
500 kHz  
tw  
µs  
µs  
µs  
µs  
µs  
µs  
µs  
tsu(DATACLK)  
tH(CLKDATA)  
tw(DATA)  
1
Data hold time  
1
Latch pulse width  
Latch setup time  
Latch hold time  
1
ts(LATCHDATA)  
tH(CLKLATCH)  
tw(XRST)  
1
1
Reset pulse width  
1
—18—  
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