CXA1390AQ/AR
PIn
No.
Voltage
Equivalent circuit
Description
Symbol
Level adjustment pin of high
luminance detection pin of the
input signal
8
CS CCD SL
Gain adjustment pin of input
signal high luminance part
9
CS CCD GC
CSAGC GC
CSAGC SL
IRIS LEVEL
IRIS GC
Gain adjustment pin of high
luminance port after AGC
11
12
21
22
25
31
32
8
9
Level adjustment pin of high
luminance detection after AGC
11
12
21
22
25
31
32
130
(Test mode at 0V)
Adjustment pin of IRIS output
weighting (Active at WND = L)
Gain adjustment pin of IRIS
output
Adjustment pin of DET output
weighting (Active at WND = L)
DET LEVEL
AGC CONT
AGC MAX
AGC amplifier gain
adjustment pin
AGC amplifier MAX gain
adjustment pin
CLP1 pulse input pin
Active at H (OPB clamp)
13
14
15
36
CLP1
P BLK
WND
CLP4
130
13
14
Pre BLK pulse input pin
Active at L
H: 4V and above
L: 1V and below
Window pulse input pin
Active at L
130
15
36
CLP4 pulse input pin
Active at H
Regulator output pin
(Used for the formation of
AGC and IRIS loop)
16
VG OUT
2.6 to 3.1V
16
100µA
Operation amplifier non
inverted input pin
OP IN +
OP IN –
28
29
130
130
28
1 to 3.3V
Operation amplifier inverted
input pin
29
– 3 –
SONY [ SONY CORPORATION ]
