SN8P2604A
8-Bit Micro-Controller
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD
3V
5V
Internal Low RC Freq.
16KHz
Watchdog Overflow Time
512ms
256ms
32KHz
Note:
1. If watchdog is “Always_On” mode, it keeps running event under power down mode or green
mode.
2. For S8KD ICE simulation, clear watchdog timer using “@RST_WDT” macro is necessary. Or
the S8KD watchdog would be error.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
Bit 6
WDTR6
W
Bit 5
WDTR5
W
Bit 4
WDTR4
W
Bit 3
WDTR3
W
Bit 2
WDTR2
W
Bit 1
WDTR1
W
Bit 0
WDTR0
W
0
0
0
0
0
0
0
0
¾
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
B0MOV
…
A, #5AH
WDTR, A
; Clear the watchdog timer.
…
CALL
CALL
…
SUB1
SUB2
…
JMP
MAIN
SONiX TECHNOLOGY CO., LTD
Page 72
Version 0.3
SONIX [ SONIX TECHNOLOGY COMPANY ]
