SN8P2604A
8-Bit Micro-Controller
6.10 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
P00IRQ
Trigger Event Description
P0.0 trigger controlled by PEDGE.
P01IRQ
T0IRQ
P0.1 falling edge trigger.
T0C overflow.
TC1IRQ
TC1C overflow.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
¾
Example: Check the interrupt request under multi-interrupt operation
ORG
JMP
8
; Interrupt vector
INT_SERVICE
INT_SERVICE:
INTP00CHK:
…
; Push routine to save ACC and PFLAG to buffers.
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Jump to INT0 interrupt service routine
; Check INT0 interrupt request
; Check P01IEN
; Jump check to next interrupt
; Check P01IRQ
; Jump to INT1 interrupt service routine
; Check T0 interrupt request
; Check T0IEN
; Jump check to next interrupt
; Check T0IRQ
; Jump to T0 interrupt service routine
; Check TC1 interrupt request
; Check TC1IEN
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTP01CHK
FP00IRQ
INTP00
INTP01CHK:
INTT0CHK:
INTTC1CHK:
INT_EXIT:
B0BTS1
JMP
B0BTS0
JMP
FP01IEN
INTT0CHK
FP01IRQ
INTP01
B0BTS1
JMP
B0BTS0
JMP
FT0IEN
INTTC1CHK
FT0IRQ
INTT0
B0BTS1
JMP
B0BTS0
JMP
FTC1IEN
INT_EXIT
FTC1IRQ
INTTC1
; Jump to exit of IRQ
; Check TC1IRQ
; Jump to TC1 interrupt service routine
…
; Pop routine to load ACC and PFLAG from buffers.
; Exit interrupt vector
RETI
SONiX TECHNOLOGY CO., LTD
Page 67
Version 0.3
SONIX [ SONIX TECHNOLOGY COMPANY ]
