SN8P2604A
8-Bit Micro-Controller
4.3 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
0
-
Bit 5
0
-
Bit 4
CPUM1
R/W
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
Bit 0
0
-
STPHX
R/W
0
-
-
-
0
0
0
-
Bit 1
STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2
CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3]
CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
¾
¾
Example: Stop high-speed oscillator
B0BSET FSTPHX
; To stop external high-speed oscillator only.
Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal
low-speed oscillator will be stopped.
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
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Page 49
Version 0.3
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