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SN8P26042A 参数 Datasheet PDF下载

SN8P26042A图片预览
型号: SN8P26042A
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 101 页 / 733 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2604A  
8-Bit Micro-Controller  
2.1.4.4 PROGRAM FLAG  
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.  
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and  
watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD36 bits indicate LVD detecting  
power voltage status.  
086H  
PFLAG  
Read/Write  
After reset  
Bit 7  
NT0  
R/W  
-
Bit 6  
NPD  
R/W  
-
Bit 5  
LVD36  
R
Bit 4  
LVD24  
R
Bit 3  
Bit 2  
C
R/W  
0
Bit 1  
DC  
R/W  
0
Bit 0  
Z
R/W  
0
-
-
-
0
0
Bit [7:6] NT0, NPD: Reset status flag.  
NT0  
0
0
1
1
NPD  
Reset Status  
Watch-dog time out  
Reserved  
Reset by LVD  
Reset by external Reset Pin  
0
1
0
1
Bit 5  
Bit 4  
Bit 2  
LVD36: LVD 3.6V operating flag and only support LVD code option is LVD_H.  
0 = Inactive (VDD > 3.6V).  
1 = Active (VDD <= 3.6V).  
LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M.  
0 = Inactive (VDD > 2.4V).  
1 = Active (VDD <= 2.4V).  
C: Carry flag  
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result  
0.  
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison  
result < 0.  
Bit 1  
Bit 0  
DC: Decimal carry flag  
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.  
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.  
Z: Zero flag  
1 = The result of an arithmetic/logic/branch operation is zero.  
0 = The result of an arithmetic/logic/branch operation is not zero.  
’
Note: Refer to instruction set table for detailed information of C, DC and Z flags.  
SONiX TECHNOLOGY CO., LTD  
Page 27  
Version 0.3  
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