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SN8P26042A 参数 Datasheet PDF下载

SN8P26042A图片预览
型号: SN8P26042A
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 101 页 / 733 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
 浏览型号SN8P26042A的Datasheet PDF文件第18页浏览型号SN8P26042A的Datasheet PDF文件第19页浏览型号SN8P26042A的Datasheet PDF文件第20页浏览型号SN8P26042A的Datasheet PDF文件第21页浏览型号SN8P26042A的Datasheet PDF文件第23页浏览型号SN8P26042A的Datasheet PDF文件第24页浏览型号SN8P26042A的Datasheet PDF文件第25页浏览型号SN8P26042A的Datasheet PDF文件第26页  
SN8P2604A  
8-Bit Micro-Controller  
2.1.2 CODE OPTION TABLE  
Code Option  
Content  
Function Description  
Low cost RC for external high clock oscillator and XOUT becomes to  
Fcpu output pin.  
RC  
Low frequency, power saving crystal (e.g. 32.768KHz) for external high  
clock oscillator.  
High speed crystal /resonator (e.g. 12MHz) for external high clock  
oscillator.  
32K X’tal  
12M X’tal  
High_Clk  
4M X’tal  
Always_On  
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.  
Watchdog timer always on even in power down and green mode.  
Enable watchdog timer. Watchdog timer stops in power down mode and  
green mode.  
Disable Watchdog function.  
Instruction cycle is oscillator clock.  
Watch_Dog  
Fcpu  
Enable  
Disable  
Fosc/1  
Notice: In Fosc/1, Noise Filter must be disabled.  
Instruction cycle is 2 oscillator clocks.  
Notice: In Fosc/2, Noise Filter must be disabled.  
Instruction cycle is 4 oscillator clocks.  
Instruction cycle is 8 oscillator clocks.  
Enable External reset pin.  
Enable P0.2 input only without pull-up resister.  
Enable ROM code Security function.  
Disable ROM code Security function.  
Enable Noise Filter and the Fcpu is Fosc/4~Fosc/8.  
Disable Noise Filter and the Fcpu is Fosc/1~Fosc/8.  
LVD will reset chip if VDD is below 2.0V  
Fosc/2  
Fosc/4  
Fosc/8  
Reset  
Reset_Pin  
Security  
P02  
Enable  
Disable  
Enable  
Disable  
LVD_L  
Noise_Filter  
LVD will reset chip if VDD is below 2.0V  
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.  
LVD will reset chip if VDD is below 2.4V  
Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.  
LVD_M  
LVD_H  
LVD  
’
Note:  
1. In high noisy environment, enable “Noise Filter” and set Watch_Dog as “Always_On”  
is strongly recommended. Enable “Noise_Filter” will limit the Fcpu = Fosc/4 ~ Fosc/8.  
2. If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog”  
automatically.  
3. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the  
Fosc is internal low clock).  
SONiX TECHNOLOGY CO., LTD  
Page 22  
Version 0.3  
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