SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
2.5 CODE OPTION TABLE
The code option is the system hardware configurations including oscillator type, watchdog timer operation, LVD option,
reset pin option and OTP ROM security control. The code option items are as following table:
Code Option
Content
Function Description
High speed internal 16MHz RC. XIN/XOUT pins are bi-direction GPIO
mode.
IHRC_16M
Low cost RC for external high clock oscillator. XIN pin is connected to RC
oscillator. XOUT pin is bi-direction GPIO mode.
RC
High_Clk
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
32K X‟tal
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
12M X‟tal
4M X‟tal
Fhosc/4
Fhosc/8
Fhosc/16
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Instruction cycle is 4 oscillator clocks.
Instruction cycle is 8 oscillator clocks.
Fcpu
Instruction cycle is 16 oscillator clocks.
Watchdog timer is always on enable even in power down and green
mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Always_On
Enable
Watch_Dog
Disable
Reset
P04
Enable
Disable
LVD_L
Disable Watchdog function.
Enable External reset pin.
Enable P0.4 input only without pull-up resister.
Enable ROM code Security function.
Disable ROM code Security function.
LVD will reset chip if VDD is below 2.0V
LVD will reset chip if VDD is below 2.0V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD will reset chip if VDD is below 2.4V
Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.
LVD will reset chip if VDD is below 3.6V
Reset_Pin
Security
LVD_M
LVD
LVD_H
LVD_MAX
2.5.1 Fcpu code option
Fcpu means instruction cycle of normal mode (high clock). In slow mode, the system clock source is internal low speed
RC oscillator. The Fcpu of slow mode isn‟t controlled by Fcpu code option and fixed Flosc/4 (16KHz/4 @3V, 32KHz/4
@5V).
2.5.2 Reset_Pin code option
The reset pin is shared with general input only pin controlled by code option.
Reset: The reset pin is external reset function. When falling edge trigger occurring, the system will be reset.
P04: Set reset pin to general input only pin (P0.4). The external reset function is disabled and the pin is input pin.
2.5.3 Security code option
Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not
dumped complete ROM contents.
SONiX TECHNOLOGY CO., LTD
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Version 2.0
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