SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
2.2 DATA MEMORY (RAM)
128 X 8-bit RAM
Address
RAM Location
000h
RAM Bank 0
“
“
General Purpose Area
“
07Fh
080h
BANK 0
080h~0FFh of Bank 0 store system
registers (128 bytes).
“
“
“
System Register
0FFh
End of Bank 0
The 128-byte general purpose RAM is in Bank 0. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1,
b0bset…) to control Bank 0 RAM in non-zero RAM bank condition directly.
2.2.1 SYSTEM REGISTER
2.2.1.1 SYSTEM REGISTER TABLE
0
L
1
H
2
R
3
Z
4
Y
5
-
6
7
-
8
-
9
-
A
-
B
-
C
-
D
-
E
-
F
-
PFLAG
8
9
-
-
-
-
-
-
-
-
-
-
-
-
CMDB0 CMDB1 CM0M CM1M CM2M OPM
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P4CON
-
-
A
B
C
D
E
F
PEDGE
-
ADM
P1M
P1
ADB
ADR
ADT
P4M
P4
-
-
-
P0M
-
P1W
P0
-
-
-
-
-
-
-
-
-
-
-
INTRQ INTEN OSCM
WDTR TC0R
PCL
PCH
STKP
-
-
T0M
T0C
-
TC0M TC0C
BZM
-
-
-
-
-
P0UR P1UR
P4UR
-
@HL
@YZ
TC0D
-
-
STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
2.2.1.2 SYSTEM REGISTER DESCRIPTION
H, L = Working, @HL addressing register.
R = Working register and ROM look-up data buffer.
CMDB0 = Comparator output de-bounce control register 0.
CM0M = Comparator 0 mode register.
CM2M = Comparator 2 mode register.
P4CON = P4 configuration register.
Y, Z = Working, @YZ and ROM addressing register.
PFLAG = Special flag register.
CMDB1 = Comparator output de-bounce control register 1.
CM1M = Comparator 1 mode register.
OPM = OP amp 0~2 mode register.
ADM = ADC mode register.
ADB = ADC data buffer.
ADT = ADC offset calibration register.
INTRQ = Interrupt request register.
ADR = ADC resolution select register.
PEDGE = P0.0, P0.1, P0.2 edge direction register.
INTEN = Interrupt enable register.
OSCM = Oscillator mode register.
WDTR = Watchdog timer clear register.
Pn = Port n data buffer.
PCH, PCL = Program counter.
PnM = Port n input/output mode register.
PnUR = Port n pull-up resister control register.
T0M = T0 mode register.
T0C = T0 counting register.
TC0M = TC0 mode register.
TC0C = TC0 counting register.
TC0R = TC0 auto-reload data buffer.
BZM = 2K/4K buzzer mode register.
@YZ = RAM YZ indirect addressing index pointer.
STK0~STK7 = Stack 0 ~ stack 7 buffer.
TC0D = TC0 duty control register.
@HL = RAM HL indirect addressing index pointer.
STKP = Stack pointer buffer.
SONiX TECHNOLOGY CO., LTD
Page 21
Version 2.0
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