SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
Comparator supports interrupt function. The interrupt trigger condition can be selected through CM1G bit including
rising edge and falling edge. If CM1G = 0, comparator output trigger edge is falling edge. If CM1G = 1, comparator
output trigger edge is rising edge. The edge detection is from comparator output signal through delay processor. When
comparator output edge event occurs and equal CM1G condition, CM1IRQ flag is issued. If CM1IEN = 1, program
counter points to interrupt vector to execute interrupt service routine.
CM1OUT
CM1IRQ, CM1G=0 falling edge
CM1IRQ sets as falling edge.
CM1IRQ sets as falling edge.
CM1IRQ, CM1G=1 rising edge
CM1IRQ sets as rising edge. CM1IRQ sets as rising edge.
*. CM1IRQ is cleared by program.
Comparator 1 compares positive terminal‟s voltage and negative terminal‟s voltage, and then output result to output pin.
When V+ > V-, comparator outputs high status. When V+ < V-, comparator outputs low status. Comparator output
terminal builds in delay control block to achieve output hysteresis to filter output transition condition. The delay option
has 16-step including no delay, 2/Fcpu, 4/Fcpu, 6/Fcpu, 8/Fcpu, 10/Fcpu, 14/Fcpu, 16/Fcpu, 18/Fcpu, 20/Fcpu,
22/Fcpu, 24/Fcpu, 26/Fcpu, 28/Fcpu, 30/Fcpu controlled by CM1D[3:0] bits.
0000b
No
0001b
2/Fcpu
0010b
4/Fcpu
0011b
6/Fcpu
0100b
0101b
0110b
0111b
CM1D[2:0]
8/Fcpu 10/Fcpu 12/Fcpu 14/Fcpu
Delay time (us)
Fcpu=Fhosc/4
0
0.5
1
1.5
2
2.5
3
3.5
=16MHz/4=4MHz
Delay time (us)
Fcpu=Fhosc/16
=16MHz/16=1MHz
0
2
4
6
8
10
12
14
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
CM1D[2:0]
16/Fcpu 18/Fcpu 20/Fcpu 22/Fcpu 24/Fcpu 26/Fcpu 28/Fcpu 30/Fcpu
Delay time (us)
Fcpu=Fhosc/4
=16MHz/4=4MHz
Delay time (us)
Fcpu=Fhosc/16
=16MHz/16=1MHz
4
4.5
18
5
5.5
22
6
6.5
26
7
7.5
30
16
20
24
28
CM1P
CM1N
CM1OUT without delay.
CM1OUT with delay.
The delay time is controlled by CM1D[3:0] bits.
SONiX TECHNOLOGY CO., LTD
Page 97
Version 2.0
SONIX [ SONIX TECHNOLOGY COMPANY ]
