SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
8.3.4 TC0 Pulse Generator Function
TC0 timer builds in pulse generator function. The pulse generator outputs a pulse, and the pulse width is decided by
TC0 timer‟s interval time. The pulse generator is controlled by TC0PO bit. When TC0PO = 0, TC0 is normal timer mode
or PWM function mode. When TC0PO = 1, TC0 is pulse generator mode. The pulse generator needs a start trigger
signal to control TC0 counter and pulse signal output. When TC0PO is set as “1”, TC0 counter keeps stopping, and
TC0C/TC0R registers‟ value is set by program. TC0C value decides the pulse width. When the trigger event occurs,
TC0 counter starts to count, and pulse output pin outputs pulse status controlled TC0DIR. When TC0 counter
overflows, pulse signal finishes and changes to idle status. The TC0C stops counting and reloads new value through
TC0R register. In pulse generator mode, the TC0IRQ is issued as TC0 counter overflow. During pulse generator
operating, to change pulse width is through TC0R, not TC0C, or the pulse width would be error.
The pulse output control signal includes two trigger sources, and CM0SF bit controls TC0 pulse generator trigger
source. One is PWM0OUT bit (CM0SF=0), and the other is comparator 0 output edge (CM0SF=1). If the trigger source
is PWM0OUT bit, set PWM0OUT bit to output pulse signal by program, and PWM0OUT bit is cleared as TC0 counter
overflow. To output next pulse is to set PWM0OUT bit by program again.
TC0 Rate=Fhosc/2=8MHz @Fhosc=16MHz
TC0C/TC0R
Pulse Width (ns)
0x00
31875
0x01
31750
…
…
0xFE
125
0xFF
0
TC0 Rate=Fhosc/4=4KHz @Fhosc=16MHz
TC0C/TC0R
Pulse Width (us)
0x00
63750
0x01
63500
…
…
0xFE
250
0xFF
0
TC0 Rate=Fhosc/256=62.5KHz @Fhosc=16MHz
TC0C/TC0R
Pulse Width (us)
0x00
4080
0x01
4064
…
…
0xFE
16
0xFF
0
TC0 Rate=Fcpu/2=0.5MHz @Fcpu=Fhosc/16=16MHz/16=1MHz
TC0C/TC0R
Pulse Width (us)
0x00
510
0x01
508
…
…
0xFE
2
0xFF
0
TC0 Rate=Fcpu/256=3.90625KHz @Fcpu=Fhosc/16=16MHz/16=1MHz
TC0C/TC0R
Pulse Width (us)
0x00
65280
0x01
65024
…
…
0xFE
256
0xFF
0
TC0PO=1, CM0SF=0: TC0ENB must be set as “1”. TC0 8-bit binary up counter is controlled by PWM0OUT
bit. If PWM0OUT bit is set as “1” by program, TC0 starts to count. If TC0 overflows, TC0 stops counting,
PWM0OUT bit is cleared automatically, TC0IRQ is issued, and TC0C reloads new value from TC0R. It is
necessary to set PWM0OUT = 1 by program making TC0 counts again.
0xF
F
TC0 stops counting. TC0C =
TC0R.
Initial Value, TC0R=M
M
M+1
TC0C Counter
TC0ENB
……
TC0ENB is set by program.
TC0ENB is cleared by program.
TC0 overflows. TC0C reloads from TC0R.
PWM0OUT
Trigger Signal
PWM0OUT is set by program.
PWM0OUT is cleared as TC0 overflow.
TC0IRQ
TC0IRQ is set as TC0 overflow.
TC0IRQ is cleared by program.
Pulse Generator.
TC0DIR=0
Pulse Generator.
TC0DIR=1
If the trigger is comparator 0 output edge (rising edge and falling edge controlled by comparator control register‟s
CM0G bit), pulse starts to output as trigger edge condition occurrence. When TC0 overflows, pulse output pin returns
to idle status.
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