SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator.
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD
3V
5V
Internal Low RC Freq.
16KHz
Watchdog Overflow Time
512ms
256ms
32KHz
The watchdog timer has three operating options controlled “WatchDog” code option.
Disable: Disable watchdog timer function.
Enable: Enable watchdog timer function. Watchdog timer actives in normal mode and slow mode. In power down
mode and green mode, the watchdog timer stops.
Always_On: Enable watchdog timer function. The watchdog timer actives and not stop in power down mode and
green mode.
In high noisy environment, the “Always_On” option of watchdog operations is the strongly recommendation
to make the system reset under error situations and re-start again.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
WDTR
Read/Write
After reset
Bit 7
WDTR7
W
Bit 6
WDTR6
W
Bit 5
WDTR5
W
Bit 4
WDTR4
W
Bit 3
WDTR3
W
Bit 2
WDTR2
W
Bit 1
WDTR1
W
Bit 0
WDTR0
W
0
0
0
0
0
0
0
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
B0MOV
…
A, #5AH
WDTR, A
; Clear the watchdog timer.
CALL
CALL
…
SUB1
SUB2
JMP
MAIN
Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE.
Main:
@RST_WDT
; Clear the watchdog timer.
…
CALL
CALL
…
SUB1
SUB2
JMP
MAIN
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