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SN8P2742SDB 参数 Datasheet PDF下载

SN8P2742SDB图片预览
型号: SN8P2742SDB
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, OP-amp, Comparator 8-Bit Micro-Controller]
分类和应用:
文件页数/大小: 136 页 / 3074 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2740 Series  
ADC, OP-amp, Comparator 8-Bit Micro-Controller  
11.2 NORMAL COMPARATOR MODE  
Comparator pins are shared with GPIO controlled by CM2EN bit. When CM2EN=1, CM2N pin is enabled connected to  
comparator negative terminal. Comparator positive terminal is controlled by CM2RS[2:0] bits. When CM2RS[2:0]=000b,  
comparator positive terminal is from CM2P pin, and GPIO function is isolated. When CM2RS[2:0]=001b~111b,  
comparator positive terminal is connected to internal reference voltage source including 7-level which are 0.2*Vdd,  
0.3*Vdd, 0.4*Vdd, 0.5*Vdd, 0.6*Vdd, 0.7*Vdd, 0.8*Vdd, and CM2P pin is GPIO mode. CM2OEN controls comparator  
output connected to GPIO or not. When CM2OEN=1, comparator output terminal is connected to CM2O pin and isolate  
GPIO function. When CM2OEN=0, comparator output status can be read through CM2OUT flag and CM2O pin is  
GPIO mode.  
Internal Reference  
Voltage  
CM2P  
CM2N  
CM2O  
CM2P = GPIO  
CM2N  
+
+
Comparator  
Internal Logic  
Comparator  
Internal Logic  
Comparator  
Comparator  
-
-
CM2O  
CM2EN = 1, CM2OEN = 1, CM2RS[2:0] = 000b  
CM2EN = 1, CM2OEN = 1, CM2RS[2:0] = 001b~111b  
Internal Reference  
Voltage  
CM2P  
CM2N  
CM2P = GPIO  
CM2N  
+
+
Comparator  
Comparator  
Comparator  
Comparator  
Internal Logic  
Internal Logic  
-
-
CM2O = GPIO  
CM2O = GPIO  
CM2EN = 1, CM2OEN = 0, CM2RS[2:0] = 000b  
CM2EN = 1, CM2OEN = 0, CM2RS[2:0] = 001b~111b  
Note: The comparator enable condition is fixed CM2EN=1, or the comparator pins are GPIO mode and  
comparator is disabled.  
The CM2OUT and CM2IRQ bits indicate the comparator result. The CM2OUT shows the comparator result  
immediately, but the CM2IRQ only indicates the event of the comparator result. The event condition is controlled by  
register and includes rising edge (CM2OUT changes from low to high) and falling edge (CM2OUT changes from high  
to low) controlled by CM2G bit. When CM2G = 0, the comparator 2 interrupt trigger direction is falling edge. When  
CM2G = 1, the comparator 2 interrupt trigger direction is rising edge.  
Note: CM2OUT is comparator raw output without latch. It varies depend on the comparator process  
result. But the CM2IRQ is latch comparator output result. It must be cleared by program.  
SONiX TECHNOLOGY CO., LTD  
Page 102  
Version 2.0  
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