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SN8P27411SDG 参数 Datasheet PDF下载

SN8P27411SDG图片预览
型号: SN8P27411SDG
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, OP-amp, Comparator 8-Bit Micro-Controller]
分类和应用:
文件页数/大小: 136 页 / 3074 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2740 Series  
ADC, OP-amp, Comparator 8-Bit Micro-Controller  
9.2 NORMAL COMPARATOR MODE  
Comparator pins are shared with GPIO controlled by CM0EN bit. When CM0EN=1, CM0N pin is enabled connected to  
comparator negative terminal, and CM0P pin is enabled connected to comparator positive terminal. CM0OEN controls  
comparator output connected to GPIO or not. When CM0OEN=1, comparator output terminal is connected to CM0O  
pin and isolate GPIO function. When CM0OEN=0, comparator output status can be read through CM0OUT flag and  
CM0O pin is GPIO mode.  
CM0P  
CM0N  
CM0O  
CM0P  
CM0N  
+
+
Comparator  
Internal Logic  
Comparator  
Internal Logic  
Comparator  
Comparator  
-
-
CM0O = GPIO  
CM0EN = 1, CM0OEN = 1  
CM0EN = 1, CM0OEN = 0  
Note: The comparator enable condition is fixed CM0EN=1, or the comparator pins are GPIO mode and  
comparator is disabled.  
The CM0OUT and CM0IRQ bits indicate the comparator result. The CM0OUT shows the comparator result  
immediately, but the CM0IRQ only indicates the event of the comparator result. The event condition is controlled by  
register and includes rising edge (CM0OUT changes from low to high) and falling edge (CM0OUT changes from high  
to low) controlled by CM0G bit. When CM0G = 0, the comparator 0 interrupt trigger direction is falling edge. When  
CM0G = 1, the comparator 0 interrupt trigger direction is rising edge.  
Note: CM0OUT is comparator raw output without latch. It varies depend on the comparator process  
result. But the CM0IRQ is latch comparator output result. It must be cleared by program.  
Comparator supports interrupt function. The interrupt trigger condition can be selected through CM0G bit including  
rising edge and falling edge. If CM0G = 0, comparator output trigger edge is falling edge. If CM0G = 1, comparator  
output trigger edge is rising edge. The edge detection is from comparator output signal through delay processor. When  
comparator output edge event occurs and equal CM0G condition, CM0IRQ flag is issued. If CM0IEN = 1, program  
counter points to interrupt vector to execute interrupt service routine.  
CM0OUT  
CM0IRQ, CM0G=0 falling edge  
CM0IRQ sets as falling edge.  
CM0IRQ sets as falling edge.  
CM0IRQ, CM0G=1 rising edge  
CM0IRQ sets as rising edge. CM0IRQ sets as rising edge.  
*. CM0IRQ is cleared by program.  
SONiX TECHNOLOGY CO., LTD  
Page 90  
Version 2.0  
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