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SN8P27411SDG 参数 Datasheet PDF下载

SN8P27411SDG图片预览
型号: SN8P27411SDG
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, OP-amp, Comparator 8-Bit Micro-Controller]
分类和应用:
文件页数/大小: 136 页 / 3074 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2740 Series  
ADC, OP-amp, Comparator 8-Bit Micro-Controller  
7.5 PORT 4 ADC SHARE PIN  
The Port 4 is shared with ADC input function and no Schmitt trigger structure. Only one pin of port 4 can be configured  
as ADC input in the same time by ADM register. The other pins of port 4 are digital I/O pins. Connect an analog signal  
to COMS digital input pin, especially the analog signal level is about 1/2 VDD will cause extra current leakage. In the  
power down mode, the above leakage current will be a big problem. Unfortunately, if users connect more than one  
analog input signal to port 4 will encounter above current leakage situation. P4CON is Port4 Configuration register.  
Write 1into P4CON.n will configure related port 4 pin as pure analog input pin to avoid current leakage.  
0AEH  
P4CON  
Read/Write  
After reset  
Bit 7  
P4CON7  
R/W  
Bit 6  
P4CON6  
R/W  
Bit 5  
P4CON5  
R/W  
Bit 4  
P4CON4  
R/W  
Bit 3  
P4CON3  
R/W  
Bit 2  
P4CON2  
R/W  
Bit 1  
P4CON1  
R/W  
Bit 0  
P4CON0  
R/W  
0
0
0
0
0
0
0
0
Bit[4:0]  
P4CON[7:0]: P4.n configuration control bits.  
0 = P4.n can be an analog input (ADC input) or digital I/O pins.  
1 = P4.n is pure analog input, cant be a digital I/O pin.  
Note: When Port 4.n is general I/O port not ADC channel, P4CON.n must set to “0” or the Port 4.n digital  
I/O signal would be isolated.  
Port 4 ADC analog input is controlled by GCHS and CHSn bits of ADM register. If GCHS = 0, P4.n is general purpose  
bi-direction I/O port. If GCHS = 1, P4.n pointed by CHSn is ADC analog signal input pin.  
0B1H  
ADM  
Read/Write  
After reset  
Bit 7  
ADENB  
R/W  
Bit 6  
ADS  
R/W  
0
Bit 5  
EOC  
R/W  
0
Bit 4  
GCHS  
R/W  
0
Bit 3  
AVREFH  
R/W  
Bit 2  
CHS2  
R/W  
0
Bit 1  
CHS1  
R/W  
0
Bit 0  
CHS0  
R/W  
0
0
0
Bit 4  
GCHS: Global channel select bit.  
0 = Disable AIN channel.  
1 = Enable AIN channel.  
Bit 3  
AVREFH: ADC external high reference voltage input pin control bit.  
0 = ADC high reference voltage is from internal Vdd. P4.0 is GPIO or AIN0 pin.  
1 = Enable ADC external high reference voltage input pin from P4.0.  
Bit[2:0]  
CHS[2:0]: ADC input channels select bit.  
000 = AIN0, 001 = AIN1, 010 = AIN2, 011 = AIN3, 100 = AIN4, 101 = AIN5, 110 = AIN6, 111 = AIN7.  
Note: For P4.n general purpose I/O function, users should make sure of P4.ns ADC channel is disabled,  
or P4.n is automatically set as ADC analog input when GCHS = 1 and CHS[2:0] point to P4.n.  
SONiX TECHNOLOGY CO., LTD  
Page 72  
Version 2.0  
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