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SN8P2743SDB 参数 Datasheet PDF下载

SN8P2743SDB图片预览
型号: SN8P2743SDB
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, OP-amp, Comparator 8-Bit Micro-Controller]
分类和应用:
文件页数/大小: 136 页 / 3074 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P2740 Series  
ADC, OP-amp, Comparator 8-Bit Micro-Controller  
R1 2.011K ohm  
Vdd  
Connect to JP23's P10O Pin  
Vdd  
Vin-  
Vin+  
R1  
100K ohm  
+
_
Vout  
AIN1  
RT1  
50K ohm/  
25 degree  
Connect to JP23's P12O Pin  
R2  
Vss  
1.011K ohm  
Connect to JP23's P11O Pin  
Vss  
Vss  
12. When SN8P2743‟s OP-AMP function enable as the above figure. P12O (JP23) is OP-AMP‟s output. P11 (JP23) is  
OP-AMP‟s non-inverse. P10O (JP23) is OP-AMP‟s inverse.  
13. If user wants to measure OP-AMP V+ / V- / Vo voltage as the above figure, the real OP-AMP‟s inverse voltage is  
OP3N (JP7). The real OP-AMP‟s non-inverse voltage is OP3P (JP7). The real OP-AMP‟s output voltage is OP3O  
(JP7).  
14. Why OP-AMP connecting is different with measurement, because OP-AMP series connection with analog switch  
internal resistor (Ron).  
15. When CMP0 function enable. The CM0P/CM0N (JP17) will be external analog signal input pin. The P43O (JP23)  
will be CMP0s output result.  
16. When CMP1 function enable. The CM1P/CM1N (JP16) will be external analog signal input pin. The P42O (JP23)  
will be CMP1s output result.  
17. When CMP2 function enable. The CM2P/CM1N (JP8) will be external analog signal input pin. The P41O (JP23)  
will be CMP2s output result.  
18. When user uses CMP0~CMP2s CM0P/CM0N/CM1P/CM1N/CM2P/CM2N analog function, user must be  
connecting to JP17/JP16/JP8. When user uses CMP0~CMP2s CM0P/CM0N/CM0O/CM1P/CM1N/CM1O/CM2P/  
CM2N/CM2O logic function, user must be connecting to JP23s P02/P03/P43O/P16/P15/P42O/P14/P13/P41O.  
19. When user uses TC0 special function (Pulse generator function and TC0 clock source is Fcpu.) in ICE emulation.  
If user sets IDE breakpoint, the PWM plus generator output status will be unknown (Fcpu stop).  
20. When user uses TC0 special function (Pulse generator function and TC0 clock source is Fhosc.) in ICE emulation.  
If user sets IDE breakpoint, the PWM plus generator output will be finished (Fhosc still work). And the PWM pulse  
generator output will be back to idle status.  
21. When user uses CMP1 and CMP2s de-bounce time control (CM1D3~CM1D0, CM2D3~CM2D0 and clock source  
is Fcpu) in ICE emulation. If user sets IDE breakpoint, the CM0O output will be effected (Fcpu stop)  
22. When user uses CMP0s de-bounce time control (CM0D3~CM0D0 and clock source is Fhosc) in ICE emulation.  
If user sets IDE breakpoint, the CM0O output will be not effected (Fhosc still work).  
SONiX TECHNOLOGY CO., LTD  
Page 124  
Version 2.0  
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