SN8P2740 Series
ADC, OP-amp, Comparator 8-Bit Micro-Controller
14RAIL to RAIL OP AMPLIFER
14.1 OVERVIEW
OPEN
Vdd
GPIO
GPIO
GPIO
GPIO/OPP Pin
GPIO/OPN Pin
GPIO/OPO Pin
Vin+
Vin-
+
_
Vout
Vss
The micro-controller builds in one OP AMP which is Rail-to-Rail structure. That means the input/output voltage is real
from Vdd~Vss. The Rail-to-Rail OP AMP pins are shared with GPIO controlled by OPEN bit. When OPEN=0, OP AMP
pins are GPIO mode. When OPEN=1, GPIO pins switch to OP AMP and isolate GPIO path. OP pins selection table is
as following.
OP No.
OPEN
OP Positive Pin
All pins are GPIO mode. OP amp is disabled.
OPP (Vin+) OPN (Vin-)
OP Negative Pin
OP Output Pin
OP
OPEN=0
OPEN=1
OPO (Vout)
Note: If OP-amp disables, these pins exchange to GPIO mode and last status.
14.2 OP AMP REGISTER
09FH
OPM
Read/Write
After Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OPEN
R/W
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit 0
OPEN: OP Amp control bit.
0 = Disable. P1.0, P1.1, P1.2 are GPIO mode.
1 = Enable. P1.0, P1.1, P1.2 are OP Amp pins.
SONiX TECHNOLOGY CO., LTD
Page 116
Version 2.0
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