SN8P1600
8-bit micro-controller
MULTI-INTERRUPT OPERATION
In almost conditions, the software designer uses more than one interrupt requests. Processing multi-interrupt request
needs to set the priority of these interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. But
the IRQ flag “1” doesn’t mean the system to execute the interrupt vector. The IRQ flags can be set “1” by the events
without interrupt enable. Just only any the event occurs and the IRQ will be logic “1”. The IRQ and its trigger event
relationship is as the below table.
Interrupt Name
P00IRQ
Trigger Event Description
P0.0 trigger. OTP is falling edge.
TC0IRQ
TC1IRQ
TC0C overflow. (SN8P1602/1603)
TC1C overflow. (SN8P1604)
There are two works need to do for multi-interrupt conditions. One is to make a good priority for these interrupt
requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check
interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following.
ꢃ
Example: How do users check the interrupt request in multi-interrupt situation?
ORG
8
; Interrupt vector
B0XCH
B0MOV
B0MOV
A, ACCBUF
A, PFLAG
PFLAGBUF,A
; Store ACC value.
; Store PFLAG value
INTP00CHK:
INTTC0CHK:
INT_EXIT:
; Check INT0 interrupt request
; Check P00IEN
; Jump check to next interrupt
; Check P00IRQ
; Jump to INT0 interrupt service routine
; Check TC0 interrupt request
; Check TC0IEN
; Jump to exit of IRQ
; Check TC0IRQ
; Jump to TC0 interrupt service routine
B0BTS1
JMP
B0BTS0
JMP
FP00IEN
INTTC0CHK
FP00IRQ
INTP00
B0BTS1
JMP
B0BTS0
JMP
FTC0IEN
INT_EXIT
FTC0IRQ
INTTC0
B0MOV
B0MOV
B0XCH
A, PFLAGBUF
PFLAG,A
A, ACCBUF
; Restore PFLAG value
; Restore ACC value.
; Exit interrupt vector
RETI
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