SN8P1600
8-bit micro-controller
OSCM REGISTER DESCRIPTION
The OSCM register is an oscillator control register. It controls oscillator selection, system mode, watchdog timer clock
rate.
0CAH
OSCM
Read/Write
After reset
Bit 7
0
-
Bit 6
WDRST
R/W
Bit 5
0
-
Bit 4
0
-
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
0
Bit 0
0
-
-
0
-
-
0
0
-
STPHX: Eternal high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed
oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.
CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode.
CPUM0: CPU operating mode control bit. 0 = normal, 1 = sleep (power down) mode to turn off both high/low clock.
WDRST is watchdog timer control bits. The detail information is in watchdog timer chapter.
ꢂ
Note: The bit 0, 4, 7 of OSCM register must be “0”, or the system will be error.
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Revision 1.94
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