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SN8P1603S 参数 Datasheet PDF下载

SN8P1603S图片预览
型号: SN8P1603S
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-Bit Micro-Controller]
分类和应用: 微控制器
文件页数/大小: 94 页 / 531 K
品牌: SONIX [ SONIX TECHNOLOGY COMPANY ]
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SN8P1600  
8-bit micro-controller  
8TIMERS  
WATCHDOG TIMER (WDT)  
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into  
the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clear the  
watchdog timer (“B0BSET FWDRST“) should be executed within a certain period. If an instruction that clears the  
watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and  
system is restarted. The watchdog timer rate has two rates for high/low speed mode. WDT rate selection is handled by  
oscillator code option. The watchdog timer disables at power down mode.  
0CAH  
OSCM  
Read/Write  
After reset  
Bit 7  
0
-
Bit 6  
WDRST  
R/W  
Bit 5  
0
-
Bit 4  
0
-
Bit 3  
CPUM0  
R/W  
Bit 2  
CLKMD  
R/W  
Bit 1  
STPHX  
R/W  
0
Bit 0  
0
-
-
0
-
-
0
0
-
WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter.  
Note: The bit 0, 4, 5, 7 must be “0”, or the system will be error.  
Watchdog timer overflow table.  
Code option of High_Clk  
Watchdog timer overflow time  
1 / ( fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz  
1 / ( fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz  
4M_X’tal / 12M_X’tal / RC  
32K_X’tal  
Note: The watchdog timer can be enabled or disabled by the code option.  
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top  
of the main routine of the program.  
Main:  
B0BSET  
FWDRST  
; Clear the watchdog timer counter.  
.
.
CALL  
SUB1  
CALL  
SUB2  
.
.
.
.
.
.
JMP  
MAIN  
SONiX TECHNOLOGY CO., LTD  
Page 51  
Revision 1.94  
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