SN8P1602B
8-Bit Micro-Controller
8TIMERS
WATCHDOG TIMER (WDT)
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clears the
watchdog timer (“ B0BSET FWDRST “) should be executed within a certain period. If an instruction that clears the
watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and
system is restarted.
0CAH
OSCM
Read/Write
After reset
Bit 7
WTCKS
R/W
Bit 6
WDRST
R/W
Bit 5
0
-
Bit 4
CPUM1
R/W
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
0
Bit 0
0
-
0
0
-
0
0
0
-
WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter.
WTCKS: Watchdog clock source select bit 0 = Fcpu, 1 = internal RC low clock.
Watchdog timer overflow table.
WTCKS CLKMD
Code Option
Watchdog Timer Overflow Time
1 / ( Fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz
1 / ( Fcpu ÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz
1 / ( Fcpu ÷ 214 ÷ 16 ) = 65.5s, Fosc=16KHz@3V
1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V
0
0
0
1
-
0
0
1
-
4M_X’tal / 12M_X’tal / RC
32K_X’tal
-
-
-
Enable Int_16K_RC
1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V
ꢀ
Note: The watchdog timer can be enabled or disabled by the code option. If disabled, the watchdog
timer can also be served as fixed-period timer by checking the NT0 flag.
ꢁ
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
B0BSET
FWDRST
; Clear the watchdog timer counter.
.
.
CALL
SUB1
CALL
SUB2
.
.
.
.
.
.
JMP
MAIN
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Page 49
Version 1.1
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