SN8P1602B
8-Bit Micro-Controller
OSCM REGISTER DESCRIPTION
The OSCM register is an oscillator control register. It controls oscillator status, system mode, watchdog timer clock
rate.
0CAH
OSCM
Read/Write
After reset
Bit 7
WTCKS
R/W
Bit 6
WDRST
R/W
Bit 5
0
-
Bit 4
CPUM1
R/W
Bit 3
CPUM0
R/W
Bit 2
CLKMD
R/W
Bit 1
STPHX
R/W
0
Bit 0
0
-
0
0
-
0
0
0
-
STPHX: External high-speed oscillator control bit. 0 = free run, 1 = stop. This bit only controls external high-speed
oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.
CLKMD: System high/Low clock mode: bit 0 = normal (dual) mode, 1 = slow mode.
CPUM1, CPUM0: CPU operating mode control bit:
00 = normal
01 = sleep (power down) mode
10 = green mode
11 = reserved.
WDRST: Watchdog timer reset bit
0 = Non-reset
1 = clear the watchdog timer’s counter.
Please refer to the “watchdog timer chapter” for detailed information.
WTCKS: Watchdog clock source
0 = Fcpu
1 = internal RC low clock
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